Turning to FIG. 1, a conventional telescopic amplifier 100 can be seen. As shown, this telescopic amplifier 100 generally comprises a differential input pair (which generally comprises transistors Q2 and Q7) and several bias networks (which generally comprise cascoded transistor pairs Q1/Q6, Q3/Q8, Q4/Q9, and Q5/Q10). These bias networks are typically configured as current minors (each being coupled to a diode-connected transistor) or may be configured so that biases BIAS1 to BIAS4 are bias voltages. Generally, for high speed applications (i.e., greater than 10 GHz), parasitics (such as parasitic capacitances) can become problematic. In particular, parasitic capacitances resulting from configuration of transistors Q1 to Q4 and Q6 to Q9 can cause signal degradation.
Looking first to the internal nodes between transistors Q1 to Q3 and Q6 to Q8, bias network Q3/Q8 and differential pair Q2/Q7 introduce a parasitic pole (which is typically at a ratio of transconductance to parasitic capacitance CP). The parasitic capacitance CP is generally a linear combination of the gate-drain, source/drain-body, and gate-source capacitances of transistors Q2, Q3, Q7 and Q8 (represented by parasitic capacitors CP1 to CP6 for the sake of simplicity). Typically, with a current of 1 mA in each branch, a transconductance of 10 mS, and a total parasitic capacitance of 450 fF, there is a pole at 3.5 GHz, and, with a current of 600 μA in each branch, a transconductance of 6 mS, and, because there is a total parasitic capacitance of 450 fF, there is a pole at 2.1 GHz. This parasitic capacitance is usually large due to a low input referred noise limitation imposed on the amplifier 100. Thus, there is a need to compensate for the pole introduced by the parasitic capacitance of bias network Q3/Q8 and differential pair Q2/Q7.
Turning to the input terminals INP and INM, each of the transistors Q2 and Q7 has a gate-drain parasitic capacitance (represented by parasitic capacitors CP1 and CP3). These gate-drain parasitic capacitances CP1 and CP3 result in a right-half plane zero, which can be at (for example) about 20 GHz (i.e., gmdiff/CP). Thus, there is a need to compensate for the zero introduced by the parasitic capacitance of the differential input pair Q2/Q7.
An example of a conventional circuit is U.S. Patent Pre-Grant Publ. Non. 2002/0024382.